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CY2285
100-MHz Pentium(R)II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs
Features
* Mixed 2.5V and 3.3V operation * Complete clock solution for Pentium(R) II, and other similar processor-based motherboards -- Two CPU clocks at 2.5V up to 100 MHz -- Six synchronous PCI clocks, one free-running -- Two 3.3V Reference clocks at 14.318 MHz -- One 3.3V USB clock running at 48 MHz -- One 3.3V USB/IO clock running at 48 MHz/24 MHz Spread Spectrum clocking for EMI control 1.5-4.0 ns delay between CPU and PCI clocks Power-down, CPU stop and PCI stop pins Low skew outputs, 175 ps between CPU clocks Early PCI clock leads PCI by 1-4 ns (-2 option) DIV4 allows dynamic shifting of CPU and PCI clocks from the default frequency to default/4 (-2 option) * Factory-EPROM programmable output drive and slew rate for EMI customization * Available in space-saving 28-pin SSOP package * * * * * * The CY2285 possesses power-down, CPU stop, and PCI stop pins for power management control. The signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2285-2 features an early PCI clock which leads the other PCI clocks by 1-4 ns. The CY2285-2 also features a DIV4 pin which allows for dynamic shifting of CPU and PCI clocks from the default frequency to the default/4.
CY2285 Selector Guide
Clock Outputs CPU (66, 100 MHz) PCI (CPU/2, CPU/3 MHz) Ref. (14.318 MHz) USB (48 MHz) USB/IO (48 MHz/24 MHz selectable) CPU-PCI delay EPCI-PCI delay Spread Spectrum CY2285-1 2 6[1] 2 1 1 CY2285-2 2 7[1, 2] 2 1 N/A CY2285-3 2 6[1] 1 1 1
Functional Description
The CY2285 is a clock synthesizer/driver for Pentium II, or other similar processor-based mobile PCs requiring up to 100-MHz support. The CY2285 outputs two CPU clocks at 2.5V. There are six PCI clocks, running at one-half or one-third the CPU clock frequency of 66.6 MHz and 100 MHz respectively. One of the PCI clocks is free-running. Additionally, the part outputs two 3.3V reference clocks at 14.318 MHz. The CY2285 provides incorporates the Intel(R)-defined spread spectrum features. It provides a -0.6% downspread on the CPU and PCI clocks, which can help reduce EMI in certain high-speed systems.
1.5-4.0 ns N/A
1.5-4.0 ns 1.0-4.0 ns
1.5-4.0 ns N/A
-0.6% -0.6% -0.6% Downspread Downspread Downspread
Notes: 1. One free-running PCI clock. 2. One early PCI clock. SPREAD (-2,-3 option)
Logic Block Diagram
DIV4 XTALIN
XTALOUT
14.318 MHz OSC. CPU PLL /4 STOP LOGIC Divider
REF0/SPREAD REF0 (-2 option) REF1/SEL48 REF1 (-2,-3 option) VDDREF CPUCLK [0-1] VDDCPU EPCICLK (-2 option)
EPROM Delay STOP LOGIC
PWR_DWN
VDDPCI PCICLK [1-5] VDDPCI PCICLK_F VDDPCI
CPU_STOP PCI_STOP
SYS PLL
USBCLK VDD48 USB_IOCLK/TS (-1 option) USBCLK/SEL100/66 (-2 option) VDD48
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 June 30, 1999
CY2285
Pin Configurations
SSOP Top View
VSSREF XTAL_IN XTAL_OUT PCICLK_F PCICLK1 PCICLK2 VSSPCI VDDPCI PCICLK3 PCICLK4 PCICLK5 VDD48 USBCLK USB_IOCLK/TS 1 2 3 4 5 CY2285-1 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDREF REF1/SEL48 REF0/SPREAD VDDCPU CPUCLK0 CPUCLK1 VSSCPU VSSCORE PCI_STOP VDDCORE CPU_STOP PWRDWN SEL100 VSS48 REF0 XTAL_IN XTAL_OUT PCICLK_F PCICLK1 PCICLK2 VSSPCI VDDPCI PCICLK3 PCICLK4 PCICLK5 EPCICLK VDD48 USBCLK/SEL100/66 1 2 3 4 5 CY2285-2 6 7 8 9 10 11 12 13 14
SSOP Top View
28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDREF REF1 SPREAD VDDCPU CPUCLK0 CPUCLK1 VSSCPU VSSCORE PCI_STOP VDDCORE CPU_STOP PWRDWN DIV4 VSS48 VSSREF XTAL_IN XTAL_OUT PCICLK_F PCICLK1 PCICLK2 VSSPCI VDDPCI PCICLK3 PCICLK4 PCICLK5 VDD48 USBCLK USB_IOCLK/TS 1 2 3 4 5
SSOP Top View
28 27 26 25 24 CY2285-3 23 22 21 20 19 18 17 16 15 VDDREF REF1/SEL48 SPREAD VDDCPU CPUCLK0 CPUCLK1 VSSCPU VSSCORE PCI_STOP VDDCORE CPU_STOP PWRDWN SEL100 VSS48
6 7 8 9 10 11 12 13 14
Pin Summary: CY2285-1, CY2285-3
Name VDD VDDCPU VSS XTALIN[3] XTALOUT
[3]
Pins 8, 12, 19, 28 25 1, 7, 15, 21, 22 2 3 20 18 17 16 23, 24 5, 6, 9, 10, 11 4 26 (-1 option)
Description 3.3V Power supply voltage 2.5V Power supply for CPU clocks Ground Reference crystal input Reference crystal feedback Active LOW control input to stop PCI clocks Active LOW control input to stop CPU clocks Active LOW control input to power down device Select for enabling 100-MHz or 66-MHz CPU clock HIGH = 100 MHz, LOW = 66 MHz 2.5V CPU clock outputs 3.3V PCI clock outputs 3.3V Free-running PCI clock output 3.3V 14.318-MHz reference clock output and power-on spread spectrum enable strap option. Strap LOW = Spread Sprectrum enable Strap HIGH = Spread Spectrum disable Active LOW control input to enable spread spectrum 3.3V 14.318-MHz reference clock output and power-on 48-/24-MHz select strap option. Strap LOW = 48 MHz on pin14 Strap HIGH = 24 MHz on pin14 3.3V 48-MHz USB clock output 3.3V 48-MHz or 24-MHz output and three-state strapping option. Strap LOW = Enter three-state mode for testing Strap HIGH = Normal Operation
PCI_STOP CPU_STOP PWR_DWN SEL100 CPUCLK[0:1] PCICLK[1:5] PCICLK_F REF0/SPREAD
SPREAD REF1/SEL48
26 (-3 option) 27
USBCLK USB_IOCLK/TS
13 14
Note: 3. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
2
CY2285
Pin Summary: CY2285-2
Name VDD VDDCPU VSS XTALIN
[3]
Pins 8, 13, 19, 28 25 7, 15, 21, 22 2 3 20 18 17 16 23, 24 5, 6, 9, 10, 11 4 12 1 27 14
Description 3.3V Power supply 2.5V Power supply Ground Reference crystal input Reference crystal feedback Active LOW control input to stop PCI clocks Active LOW control input to stop CPU clocks Active LOW control input to power down device Active LOW control input to enable divide-by-four option on CPU and PCI clocks 2.5V CPU clock outputs 3.3V PCI clock outputs 3.3V Free-running PCI clock output 3.3V Early PCI clock output (Not Free-running) 3.3V 14.318-MHz reference clock output 3.3V 14.318-MHz reference clock output 3.3V 48-MHz USB clock output or select input and frequency select strap option (use 10-k external strap resistor) Strap LOW = 66.6-MHz CPU Frequency Strap HIGH = 100-MHz CPU Frequency Active LOW control input to enable Spread Spectrum
XTALOUT[3] PCI_STOP CPU_STOP PWR_DWN DIV4 CPUCLK[0:1] PCICLK[1:5] PCICLK_F EPCICLK REF0 REF1 USBCLK/SEL100/66
SPREAD
26
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK Target Frequency Actual Frequency (MHz) (MHz) 66.67 100 66.654 99.77 PPM -240 -2300
Power Management Logic
CPU_STOP X 0 0 1 1 PCI_STOP X 0 1 0 1 PWR_DWN 0 1 1 1 1 CPUCLK Low Low Low Running Running PCICLK Low Low Running Low Running PCICLK_F Low Running Running Running Running Other Clocks Low Running Running Running Running Osc. Off PLLs Off
Running Running Running Running Running Running Running Running
3
CY2285
Function Table: CY2285-1
SEL100 X 0 0 1 1 SEL48[4] X 1 0 1 0 TS[4] 0 1 1 1 1 SPREAD[4] X 1 (no spread) 0 (-0.6% downspread) 1 (no spread) 0 (-0.6% downspread) CPUCLK[0:1] Hi-Z 66.6 MHz 66.6 MHz 100 MHz 100 MHz PCICLK[1:5], PCICLK_F Hi-Z 33.3 MHz 33.3 MHz 33.3 MHz 33.3 MHz USB_IOCLK Hi-Z 24 MHz 48 MHz 24 MHz 48 MHz USBCLK Hi-Z 48 MHz 48 MHz 48 MHz 48 MHz REFCLK [0-1] Hi-Z 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz
Function Table: CY2285-2
SEL100/66[4] 0 0 1 1 0 0 1 1 SPREAD 0 (-0.6% downspread) 1 (no spread) 0 (-0.6% downspread) 1 (no spread) 0 (-0.6% downspread) 1 (no spread) 0 (-0.6% downspread) 1 (no spread) DIV4 1 1 1 1 0 0 0 0 CPUCLK [0:1] 66.67 MHz 66.67 MHz 100 MHz 100 MHz 16.67 MHz 16.67 MHz 25.0 MHz 25.0 MHz PCICLK[1:5], PCICLK_F, EPCICLK 33.3 MHz 33.3 MHz 33.3 MHz 33.3 MHz 8.33 MHz 8.33 MHz 8.33 MHz 8.33 MHz USBCLK 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz REFCLK[0:1] 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz
Function Table: CY2285-3
SEL100 X 0 0 1 1 SEL48[4] TS[4] SPREAD[4] X 1 0 1 0 0 1 1 1 1 X 1 (no spread) 0 (-0.6% downspread) 1 (no spread) 0 (-0.6% downspread) CPUCLK[0:1] Hi-Z 66.6 MHz 66.6 MHz 100 MHz 100 MHz PCICLK[1:5], PCICLK_F Hi-Z 33.3 MHz 33.3 MHz 33.3 MHz 33.3 MHz USB_IOCLK Hi-Z 24 MHz 48 MHz 24 MHz 48 MHz USBCLK Hi-Z 48 MHz 48 MHz 48 MHz 48 MHz REFCLK1 Hi-Z 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz
Note: 4. Power-on strap option.
4
CY2285
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5 Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[5]
Parameter VDD VDDCPU TA CL CPU Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK PCICLK REF Reference Frequency, Oscillator Nominal Value 14.318 Description Analog and Digital 3.3V Supply Voltage Min. 3.135 2.375 0 Max. 3.465 2.625 70 20 30 35 14.318 MHz Unit V V C pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Except Crystal Inputs[6] Except Crystal Inputs
[6]
Test Conditions
Min. Max. Unit 2.0 0.8 V V V 0.4 2.4 V V
High-level Output Voltage VDDCPU = 2.375V Low-level Output Voltage VDDCPU = 2.375V High-level Output Voltage VDDPCI, AVDD, VDDREF = 3.135V
IOH = 12 mA IOL = 12 mA IOH = 16 mA IOH = 36 mA
CPUCLK CPUCLK REF REF[7] PCICLK REF REF[7]
2.0
IOH = 14.5 mA PCICLK
VOL
Low-level Output Voltage
VDDPCI, AVDD, VDDREF = 3.135V
IOL = 9.4 mA IOL = 9 mA IOL = 29 mA
0.4V
V
IIH IIL IOZ IDD25 IDD25 IDD33 IDDS
Input High Current Input Low Current Output Leakage Current Power Supply Current for 2.5V clocks Power Supply Current for 2.5V clocks Power Supply Current for 3.3V clocks Powerdown Current
VIH = V DD VIL = 0V Three-state VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.6 MHz VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 100 MHz VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs Current draw in powerdown state
-10 -10
+10 10 +10 70 100 170 500
A A A mA mA mA A
Notes: 5. Electrical parameters are guaranteed with these operating conditions. 6. Crystal Inputs have CMOS thresholds, nominally VDD/2. 7. CY2285-2 option only.
5
CY2285
Switching Characteristics[8] Over the Operating Range
Parameter t1 t2 t2 t2 t3 t4 t5 t6 t7 t7 t10 t11 t12 t13 Output All CPUCLK PCICLK REF CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK PCICLK, PCICLK EPCICLK, PCICLK CPUCLK PCICLK CPUCLK, PCICLK CPUCLK, PCICLK Description Output Duty Cycle
[9]
Test Conditions t1 = t1A / t1B Between 0.4V and 2.0V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.0V Between 2.0V and 0.4V Measured at 1.25V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V Measured at 1.25V Measured at 1.5V CPU and PCI clock stabilization from power-up Time for CPU, EPCI, and PCI clock frequency to change from f to f/4 after select input change
Min. 45 1.0 1.0 0.5 0.4 0.4
Typ. 50
Max. 55 4.0 4.0 2.0 1.6 1.6
Unit % V/ns V/ns V/ns ns ns ps ns ps ns ps ps ms cycles
CPU Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate REF Clock Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew PCI-PCI Clock Skew EPCI-PCI Clock Skew[7] Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time /4 Frequency Slew Time[7]
100 1.5
175 4.0 250
1.0
4.0 700 500 3 10 25
Notes: 8. All parameters specified with loaded outputs. 9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V..
6
CY2285
Switching Waveforms
Duty Cycle Timing
t1A OUTPUT t1B
All Outputs Rise/Fall Time
VDD OUTPUT t2 t3 t2 t4 0V
CPU-CPU Clock Skew
CPUCLK
CPUCLK t5
CPU-PCI Clock Skew
CPUCLK
PCICLK t6
PCI/EPCI-PCI Clock Skew
PCI/EPCICLK
PCICLK t7
CPU_STOP
CPUCLK (Internal) PCICLK (Internal) PCICLK
(Free-Running)
CPU_STOP CPUCLK (External)
7
CY2285
Switching Waveforms (continued)
PCI_STOP
CPUCLK (Internal) PCICLK (Internal) PCICLK
(Free-Running)
PCI_STOP PCICLK (External)
PWR_DOWN
CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Ordering Information
Ordering Code CY2285PVC-1 CY2285PVC-2 CY2285PVC-3 Document #: 38-00732-B Package Name O28 O28 O28 Package Type 28-Pin SSOP 28-Pin SSOP 28-Pin SSOP Operating Range Commercial Commercial Commercial
8
CY2285
Package Diagram
28-Lead (210-Mil) Shrunk Small Outline Package O28
51-85079-B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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